AI

Milan Kubavat · May 14, 2026 · -- min read

AI used well is a force multiplier for DV engineers; AI used badly is a liability that ships latent bugs. This page is a map of where AI fits across the design-and-verification lifecycle — from spec to testplan, assertions, testbenches, coverage, formal, and debug — plus the foundations, the engineering discipline, and the honest limits. Each card opens into a deep-dive.

The foundational reference is the Practitioner Playbook below. The lifecycle cards track where the 2024-2026 research actually organizes itself: published systems now exist for every stage from spec-to-testplan (Saarthi) through assertion generation (AssertLLM), testbench synthesis (HAVEN, UVM², UVMarvel), coverage closure (LLM4DV), and formal-failure root cause (FVDebug).

Foundations — Prompt, Context & Knowledge

The shift the field made in 2025: from optimizing one prompt to engineering the context, tools, retrieval, and reasoning loop. These cards are where every other technique starts.

AI Playbook for DV

Prompt, context, pair programming, debug, code gen, agentic patterns — the full reference

Prompt Engineering for DV

Spec-as-prompt, few-shot from golden examples, decomposition — for RTL and UVM alike

Context Engineering

Minimum viable context, tool-per-concept, scratchpads, stale-context pruning

RAG & Domain Knowledge

Protocol libraries, spec retrieval, knowledge graphs — curated knowledge beats raw specs

AI Across the DV Lifecycle

The task-by-task map. Published research systems now cover every stage of the verification flow — these cards track what works at each one.

Spec → Testplan

LLMs decompose specifications into human-reviewable verification plans — Saarthi, ThreatLens

Assertion & SVA Generation

Prompting, RAG, and fine-tuned routes — AutoSVA2, AssertLLM, ChIRAAG, ChipNeMo

Testbench & Stimulus Generation

HAVEN, UVM², UVMarvel — published agent systems for UVM synthesis at real coverage

Coverage Closure with AI

Closed-loop generation on uncovered bins — LLM4DV, VerilogReader, RL case studies

Formal Verification + LLMs

NL-to-SVA, assertion suggestion, formal-failure root cause — FVEval, Saarthi, FVDebug

Debug & Triage Automation

Regression-scale root-cause and repair loops — beyond the interactive pair-debug session

AI as Collaborator

The strongest empirical results in AI-for-code live in debugging and scaffolding. These cards cover the day-to-day interactive patterns.

AI as Pair Programmer

UVM scaffolding, refactor proposals, commit explanations, docs and legacy walkthroughs

Hypothesis-rank, CoT on log slices, self-debug loops, invariant-violation checks

Engineering Discipline

What keeps AI-assisted work trustworthy: honest benchmarks, hard gates, a deliberate model strategy, robust tool interfaces, and security awareness.

Code Gen Limits & Benchmarks

The 34% CVDP ceiling and the unit-test fallacy — module pass@k vs system-level truth

Validation Gates & Tech Debt

Compile + lint + smoke gates for every AI artifact; SATD tagging for AI-era debt

Fine-Tuned vs Frontier Models

Prompt-based, fine-tuned (ChipNeMo), or multi-agent — the autonomy/cost tradeoff

EDA Tool Integration

From fragile log parsing to machine-readable tool APIs — the agent-EDA interface problem

Security Verification & IP Safety

LLM-driven SoC security verification (SV-LLM, SoCureLLM) and IP-leakage cautions

Agentic Systems & Limits

Agents that reason, act, self-critique, and orchestrate — and the honest version of where all of this still fails.

Agentic Design Patterns

ReAct, Reflexion, Plan-and-Execute, multi-agent orchestration with checkpoints

The Honest Limits

Multi-cycle RTL, novel protocols, long-context degradation, the 34% ceiling

Research Reading List

The arxiv, DVCon, and DAC literature from 2024-2026, grouped by theme

Start Here

Read the AI Playbook for DV — the foundational reference covering all themes on this page.
Pick one debugging pattern from the "AI as Debugger" card and try it on your next failing test — hypothesis-rank is the lowest-friction entry.
Add a validation gate to any workflow where AI-generated code lands in your codebase — compile + lint + one smoke test minimum.