Silicon Verification: Debug

Most DV debug content shows you tool features. This page is about debug engineering — the logging discipline, correlation IDs, scientific method, DUT instrumentation, triage automation, and replay techniques that make modern debug fast, reproducible, and ready for AI assistance.

It is a deliberate fusion of two traditions: the SystemVerilog / UVM toolkit that DV engineers already use, and the systematic debugging literature from software engineering — Andreas Zeller's scientific debugging, David Agans's 9 indispensable rules, Michael Feathers's work on legacy code, and the SRE observability canon. The premise is simple: a testbench whose logs are structured is a testbench whose failures are queryable — and a queryable testbench is one that scripts can triage, dashboards can summarize, and LLMs can reason about.

Foundations — Structured Debug Data

Logs, metrics, and traces already live inside your UVM testbench — just unstructured. These four cards convert each of them into a queryable surface.

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Structured Logging

Custom uvm_report_server, JSONL sidecars, typed log records, jq pipelines

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Observability Triad

Logs, metrics, traces — the three signals your testbench already emits

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Wide Events & High-Cardinality

One row per transaction, hundreds of fields, Honeycomb-style queries

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Trace IDs & Context Propagation

UUID per sequence_item, parent-child linking, OpenTelemetry context

The Scientific Method of Debug

Zeller's Why Programs Fail reframes debugging as science: hypothesis, experiment, observation, refine. Agans's Rule 2 makes it actionable — debug starts when you can reproduce the failure deterministically.

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Hypothesis-Driven Debug

Zeller's cycle — observe, hypothesize, experiment, refine

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Reproduce-First Discipline

Agans Rule 2 — seed, plusargs, RTL hash, one-line replay artifact

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Program Slicing & Causation

Backward causation chains, dynamic slicing, Verdi RCA as discipline

Correctness — Self-Asserting Testbenches

Push correctness into the testbench itself: contracts on every interface, automated shrinking on every failure, golden references for every checker.

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Design by Contract

Preconditions, postconditions, invariants — SVA assume/assert, do_check

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Property Testing & Shrinking

CRV with shrinking — Hypothesis-style minimal repro for failing seeds

🖼️

Snapshot & Golden Files

Golden waveforms, golden logs, normalized diffs across runs

DUT Instrumentation — White-Box Observability

The DUT is not a black box once you have bind. These four cards cover non-intrusive harnessing, hang detection, and the X-state discipline that has no SWE analog.

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bind-Based DUT Harness

Non-intrusive SVA, coverage modules, shadow monitors via bind

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Seams for Legacy DUT

Feathers's seams — instrument inherited RTL without editing it

⏱️

Watchdog & Hang Detection

Per-test, per-phase, per-transaction timers, structured hang reports

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X-Propagation Discipline

Xprop modes, X-optimism vs pessimism, X-aware checking

Triage at Scale — Noise to Signal

When the regression has 10,000 fails, the first task is not debug — it is grouping. Three complementary algorithms collapse the noise.

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Error Fingerprinting

Sentry-style hashing — 10K fails collapsed into a dozen buckets

✂️

Delta Debugging (DDMIN)

Zeller's DDMIN — minimal failing transaction streams

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Regression Bisection

git bisect for RTL commits, O(log n) to find the break

Replay & Resilience

Simulation is already deterministic — treat it that way. Then deliberately inject the chaos you would otherwise wait for production silicon to surface.

⏪

Time-Travel Debug

rr/Pernosco for testbenches — snapshot, jump, query the run

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Fault Injection & Chaos

First-class fault sequences, recovery coverage, Chaos Monkey for DUTs

Process & GenAI Payoff

Once the foundations are in place, AI becomes the cheapest leverage on top of everything else — not a magic shortcut to skip the foundations.

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Blameless Postmortems

Five Whys, action items, feedback into the coverage plan

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Debug Context Bundles

Slice 200 events + bound SVA + RTL excerpt for the LLM

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AI-Assisted Debug

Failure summarization, similar-bug retrieval, next-step suggestion

Agans's 9 Indispensable Rules — Applied to DV

Understand the System. Read the spec before grep'ing the log. The waveform is not a substitute for the protocol document.
Make It Fail. Capture seed + plusargs + RTL hash + tool version into a one-line replay artifact. If you can't reproduce it, you can't debug it.
Quit Thinking and Look. Open the waveform. The signal value is truth; your mental model is a guess.
Divide and Conquer. Bisect commits, bisect transactions, bisect time. Binary search applies at every layer.
Change One Thing at a Time. Never mutate testbench, RTL, and seed in the same debug iteration. Confounded variables hide the cause.
Keep an Audit Trail. Every regression has structured logs. Every escape has a postmortem. Every bug links to its closing commit.
Check the Plug. Verify the clock, reset, plusargs, license server, and tool version before debugging logic. The trivial explanation is usually correct.
Get a Fresh View. Explain the bug to a colleague — or an LLM. Articulation finds half of bugs without the listener saying a word.
If You Didn't Fix It, It Ain't Fixed. Add a coverage point and a regression test for every closed bug. Otherwise the same bug returns wearing a different hat.

Start Here — A 3-Step Adoption Path

Add a JSON sidecar log. Extend uvm_report_server to emit a JSONL file alongside your human log. No test-code changes required.
Stamp every transaction with a UUID. Generate it in pre_randomize() and carry it through driver, monitor, and scoreboard log lines.
Pipe one failing log to an LLM. Use the bundle pattern — JSON slice (last ~200 events) + relevant RTL snippet + failing assertion. See what it catches before investing further.