UVM
Design patterns mapped to UVM verification. Each pattern includes UML diagrams, SystemVerilog implementation, and practical examples.
Creational Patterns
Factory
UVM's type_id::create(), custom factories, type overrides
Singleton
uvm_root, uvm_config_db, global resources
Builder
Complex transaction construction, fluent interfaces
Prototype
clone() methods, transaction copying, do_copy()
Abstract Factory
Protocol-family agent bundles, related component sets
Structural Patterns
Adapter
uvm_reg_adapter, reg2bus/bus2reg, register model integration
Decorator
Analysis subscribers, coverage wrappers, transaction decoration
Facade
Simplified test APIs, virtual sequences as facade
Proxy
Controlling access with register models and sequencers
Bridge
Frontdoor/backdoor register access, abstraction split from implementation
Composite
uvm_component hierarchies, sequence trees, uniform traversal
Flyweight
Shared config objects, register model handle reuse
Behavioral Patterns
Observer
Analysis ports, scoreboards, coverage collectors
Strategy
Pluggable checkers, response policies, algorithms
Chain of Responsibility
Layered sequences, protocol stacks (PCIe/USB)
Command
Sequence items as commands, request encapsulation
State Machine
Protocol FSMs, reactive agents, LTSSM
Template Method
Base sequence body(), phase hooks, callbacks
Interpreter
Constraint expressions, scripted stimulus DSLs
Iterator
Component tree traversal, sequence iteration, queue walks
Mediator
Virtual sequencers coordinating multi-agent traffic
Memento
Register mirror snapshots, simulation save/restore
Visitor
uvm_visitor, field operations across component trees