UVM

Design patterns mapped to UVM verification. Each pattern includes UML diagrams, SystemVerilog implementation, and practical examples.

Creational Patterns

🏭

Factory

UVM's type_id::create(), custom factories, type overrides

1️⃣

Singleton

uvm_root, uvm_config_db, global resources

🔧

Builder

Complex transaction construction, fluent interfaces

📋

Prototype

clone() methods, transaction copying, do_copy()

Structural Patterns

🔌

Adapter

VIP integration, legacy TB wrapping, interface conversion

🎀

Decorator

Sequence layering, adding behavior dynamically

🚪

Facade

Simplified test APIs, virtual sequences as facade

🎭

Proxy

Sequence item handles, lazy evaluation, access control

Behavioral Patterns

👁️

Observer

Analysis ports, scoreboards, coverage collectors

🎯

Strategy

Pluggable checkers, response policies, algorithms

⛓️

Chain of Responsibility

Layered sequences, protocol stacks (PCIe/USB)

📨

Command

Sequence items as commands, request encapsulation

🔄

State Machine

Protocol FSMs, reactive agents, LTSSM

📝

Template Method

Base sequence body(), phase hooks, callbacks